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TAOS tapes out mixed signal IC using Silvaco’s place and route and EDA tool flow Plano, TX and Santa Clara, CA – Monday, February 17th, 2010 Texas Advanced Optoelectronic Solutions, Inc. (TAOS), today announced the successful tape out of a mixed-signal chip developed using Silvaco’s tool flow and PDK. The mixed-signal circuit was simulated using SmartSpice and laid out using Expert. Verification was performed using Guardian LVS and DRC. The parasitic annotated netlist used for timing analysis was generated with HIPEX-RC. The large digital portion of the IC was routed using SPIDER, Silvaco’s new place and route tool. "The combination of Silvaco’s EDA tool flow, together with their excellent technical support team, allowed us to fulfill our design objectives and meet our deadlines," said Lloyd Hasley, VP of Engineering at TAOS. Hasley added, "We consider Silvaco’s support an extension to our engineering team". "SPIDER allowed us to use limited metal resources to complete routes. We regularly finish 3 metal routes with 80% + densities," said Chuck Watson, a SPIDER user. Watson added, "We revisited legacy designs completed with a third party router and were able to reroute those netlists with 50% smaller footprints. SPIDER exceeded our expectations for relative performance". "The flexibility of the SPIDER place and route tool allowed TAOS to meet their targeted area for the digital block while avoiding the extra expense of additional metal routing layers," said Michel Blanchette, lead AE at Silvaco’s Texas office.
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