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Brochure (PDF) 2.6 MB

Product Group:

Expert
Layout Editor
Guardian
DRC/LVS/NET Physical Verification
HIPEX
Full-Chip Parasitic Extraction
ClarityRLC
RLC Netlist Reduction

IC layout, DRC/LVS verification, and RC parasitic extraction environment for analog, mixed-signal and RF design engineers

Custom IC CAD

Rev. 031512_16

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