CatalystAD

SPICE Netlist to Verilog Gates Converter

The premier tool for converting transistor-level designs into verilog gate-level representations with applications in microprocessor, DSP, graphics and high-speed communication markets.

Key Features

• Provides an automated solution for generating gate-level verilog netlists and models from transistor netlists
• Ideal for reverse-engineering legacy hard IP and custom logic for design reuse and migration
• Supports HSPICE™/SPECTRE™ and DSPF hierarchical or flat netlists
• Handles all classes of CMOS/SOI design styles (standard cell, custom, static, dynamic, combinational, sequential, domino, footed, footless, self-timed, post-charged, cascode, DCVS, pass transistor, barrel-shifters, cross-bar switching structures, m-of-n logic trees, etc.)
• Controls proper modeling of wide fan-in pass-gates of 24 inputs or more, sneak paths and output path depths containing hundreds of thousands of parallel paths
• CatalystAD and AccuCore together deliver a complete verification and timing modeling solution

Rev. 010609_03