CatalystDA

Verilog Netlist to SPICE Netlist Converter

CatalystDA is a software program that translates a structural Verilog netlist into equivalent SPICE format netlist to be used for layout verification or SPICE simulation.

Key Features:

• An automated solution for generating SPICE netlists from Verilog structural description
• Accepts IEEE 1364-2001 Verilog input files
• Capable of generating netlists in Calibre extended SPICE format as well as standard SPICE format
• Performs syntax and syntactical checking of Verilog source files
• Performs a partial translation of Verilog netlists even if some module definitions are not availabl
• Automatically creates and connects SPICE power and ground nets
• Capable of handling multi-million gate Verilog netlists
• CatalystDA and Guardian LVS together deliver a complete layout verification solution

Rev. 082509_02