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CatalystDA:

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CatalystDA is a converter that translates a structural Verilog netlist into equivalent SPICE format netlist to be used for layout verification or SPICE simulation. CatalystDA can be used in place of Calibre V2LVS and provides following key features:

• CatalystDA and Guardian LVS together deliver a complete layout verification solution
• Capable of generating netlists in Calibre extended SPICE format as well as standard SPICE format
• Capable of performing a partial translation of Verilog netlists even if some module definitions are not available
• Support to use SPICE library files for interface configuration
• Automatically creates and connects SPICE power and ground nets
• Automatically replaces non-SPICE characters in conversion
• Unconnected pins can receive numbered connections with option
• Flexible power and ground net naming options
• Option to name primitive gates to resolve name conflicts
• Additional pins can be added to a subcircuit definition
• Command options can be integrated into an option file for easy reuse and better project management
• Accepts IEEE 1364-2001 Verilog input files
• Performs syntax and syntactical checking of Verilog source files
• Capable of handling multi-million gate Verilog netlists

Calibre V2LVS is the trademark of its owner.