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TCAD

Analog / AMS / RF

	   Overview
	   Gateway
	   SmartSpice
	   Verilog-A Language
	   SmartSpiceRF
	   Harmony
	   UTMOST III     
	   UTMOST IV     
	   SPAYN     
  

Custom IC CAD

	   Overview
	   Expert
	   Guardian
	   HIPEX
	   ClarityRLC
  

Interconnect Modeling

	   Overview
	   EXACT
	   QUEST
	   CLEVER
	   STELLAR
  

Digital CAD

	   Overview
	   SILOS
	   HyperFault
	   AccuCell
	   AccuCore
	   CatalystAD
	   CatalystDA
	   Spider
  

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Services

	   Overview
	   TCAD Services
	   SPICE Modeling
	   Parasitic Extraction
	   PDK Development
	   Cell Libraries and Blocks
  

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Product Roadmaps
90 Day | 1 Year | 3 Year

Gateway

3 Year Development Roadmap

Version control mechanism
Advanced SDL integration including constraints
Place & Route integration
Schematic Realization from netlists (SPICE and Verilog)

Last Revised 03/30/2012