More About HyperFault

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HyperFault is a Verilog IEEE-1364-2001 compliant fault simulator that analyzes test vectors’ ability to detect faults. Supports mixed levels of gate, behavioral, and switch with SDF timing. HyperFault can be used as a replacement for Synopsys TetraMAX ATPG, Mentor Graphics Tessent FastScan, Mentor Graphics Tessent TestKompress, Cadence Verifault, Cadence Encounter True-Time ATPG, Syntest TurboFault, Winterlogic Z01X, and provides the following key features:

• Fault simulator for IEEE 1364-2001 VERILOG language compliant designs, libraries and Programming Language Interface (PLI) test benches for mixed-level fault simulation with gate, behavioral and switch devices that do not support ATPG modeling in the libraries.
• Use when BIST and ATPG is not enough in finding interconnect faults due to efficient multi-pass, iterative fault collapsing and HyperTrophic algorithms with excellent runtimes, large design handling and automatic design partitioning across multiple CPUs.
• Fault grading models include stuck-at high/low output and Value Change Dump (VCD) input faults utilizing random fault sampling with support for Standard Delay Format (SDF) back annotation of post-route delays of the Device Under Test (DUT).
• Handles non-BIST, non-scan and partial-scan design styles for low power and critical path high speed circuits including asynchronous designs.

Synopsys TetraMAX ATPG, Mentor Graphics Tessent FastScan, Mentor Graphics Tessent TestKompress, Cadence Verifault, Cadence Encounter True-Time ATPG, Syntest TurboFault, Winterlogic Z01X are the trademarks of their respective owners.