More About
HIPEX:

Brochure (PDF) 1.9 MB

Release Notes

Manuals

Product Roadmaps
90 Day | 1 Year | 3 Year

Application Notes

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Product Family:

Guardian
DRC/LVS/NET Physical Verification

See Also::

EXACT
Full Chip LPE Rule File Generator

HIPEX performs rapid 2.5D rule-based full-chip hierarchical RC parasitic resistance & capacitance extraction of arbitrary Very-Deep-Sub-Micron (VDSM) layouts. Hipex can be used in place of StarRC, Assura ,QRC, Calibre-XRC, QuartzRC and provides the following key features:

• Seamless integration with the Expert Layout Editor and Guardian DRC / LVS for complete design/verification flow
• Built-in, state-of-the-art lumped or distributed parasitic R-only, C-only & RC extraction including coupling effects together with advanced RLC network reduction assures accurate and compact back-annotated SPICE, DSPF and SPEF netlists at either transistor or gate levels
• Supports either full-chip or select critical path net extraction enabling accurate post-layout SPICE simulation and Static Timing Analysis (STA).
• Powerful and fully customizable Lisa and JavaScript programming plus advanced metal fill handling accelerate and adapt hierarchical processing and automatically check and address any layout style irregularities at run-time
• Support in PDKs for multiple foundry processes (TSMC, UMC, Jazz/TOWER, X-Fab, Austriamicrosystems (AMS), AMI, MOSIS and many others)

Cadence Assura, Cadence QRC, Synopsys StarRC, Mentor Calibre-XRC, Magma QuartzRC are trademarks of their respective owners.