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Release Notes (Since Baseline)
Release Notes (2012 Baseline)
Product Roadmaps
90 Day | 1 Year | 3 Year

See Also:

AccuCell
Cell Characterization and Modeling
AccuCore and its Competitors
Synopsys Pathmill, Synopsys Nanotime, Synopsys PrimeTime, Synopsys HSPICE, Cadence Encounter Timing System, Cadence SPECTRE, Magma Tekton, Magma Quartz Time

AccuCore performs timing characterization of multi-million device circuits with SmartSpice accuracy and performs block and full-chip Static Timing Analysis (STA) on multi-million gate designs. AccuCore can be used as a replacement for Synopsys Pathmill, Synopsys Nanotime, Synopsys PrimeTime, Synopsys HSPICE, Cadence Encounter Timing System, Cadence SPECTRE, Magma Tekton, and Magma Quartz Time providing the following key features:

  • Generates Liberty (.lib) timing models, generates a gate-level VERILOG netlist and generates or reads DSPF files for Static Timing Analysis (STA)
  • Automated Liberty (.lib) to (.cfg) import for easy setup and scripting with various (.cfg) validation options
  • State-of-the-art strength and state-based Ordered Binary Decision Diagram (OBDD) method automatically extracts cell functions and generates optimal vectors required for accurate SPICE characterization of the latest VDSM effects including simultaneous switching
  • Includes fast API-based SmartSpice characterization engine (100% HSPICE and SPECTRE compatible)
  • Supports HSPICE, SPECTRE and ELDO as external simulators
  • ASIC flow option for easy standard cell-based flows
  • Advanced one-time multi-corner, multi-mode full path model characterization for fast Static Timing Analysis (STA)
  • Exports fully sensitized SPICE deck for selected critical paths and clock trees with measurements
  • Automatically partitions blocks into cells
  • Automatically extracts cell functions and generates vectors required for accurate SPICE characterization
  • Complete block and full-chip gate-level STA environment for rapid bottleneck analysis and timing verification
  • Powerful command set enables mixing both custom and ASIC/SoC functions in a single analysis environment
  • Enables gate-level timing checks of custom transistor level designs
  • Automatic false path elimination
  • Analyzes gated and multi-frequency clocks across multi-cycle paths
  • Supports DSPF and SDF back-annotation
  • Tcl API interface for custom reporting and analysis functions

Synopsys Pathmill, Synopsys Nanotime, Synopsys PrimeTime, Synopsys HSPICE, Cadence Encounter Timing System, Cadence SPECTRE, Magma Tekton, Magma Quartz Time and Mentor ELDO are the trademarks of their respective owners.

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