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STELLAR

3D Physics-Based RC Extractor for Large Cells

STELLAR fills the size gap between typical small cell field solvers and full chip extractors. STELLAR uses a new highly efficient fictitious domain field solver to characterize cells containing tens of thousands of active elements, providing the physics-based accuracy of a field solver with the cell size capability of a full chip extractor.

Key Features

• Use of a highly efficient fictitious domain numerical method reduces simulation time and memory requirement
  
• Correctly accounts for structures containing floating electrodes
  
• Includes SPICE netlist extractor
  
• Integrated scripting language provides user defined post-processing data manipulation
  
• Intuitive and user-friendly graphical user interface

STELLAR design flow versus the traditional flow.

Ease of Use and Adoption

• 100% Graphical User Interface driven
• Uses Silvaco’s universal parasitic back-end graphical interface
• Automatic file generation and submission to 3D field solver
• Specific graphical user interface for setting up technology files (layer connection, definition of derived layer, layer mapping ….)
• Post-processing tools like Worksheet/Optimizer for graphical result analysis
• Process preview for debugging
• 3D structure visualization using TonyPlot3D
• Advanced physical models developed and verified in collaboration with the
  leading research institute LETI

Main STELLAR GUI interface.	Backend 3D process structure used by STELLAR to calculate capacitances.
Example of simulated layout in STELLAR.

Productivity and Versatility

• Automatic grid generation during 3D parasitic extraction
• Selective area parasitic extraction enables maximum accuracy for critical layout windows
• Selective net parasitic extraction enables maximum accuracy for critical net
• Supports multi-processor machines
• Batch mode facilitates cell characterization runs
• Design of experiment capabilities for process variation analysis
• Ability to stop a simulation and restart, avoids having to re-simulate the entire circuit
• Based on a 3D process simulator including multiple dielectrics and metal capability and user specified material properties
• Tight coupling with SPICE simulator for circuit timing analysis
• Automatic halo selection for decreasing simulation time and memory
• Automatic domain decomposition algorithm for large circuit simulation
• Validation against measurements and other field solvers such as CLEVER Physics-Based Parasitic Extractor

Resulting SmartSpice transient analysis.

Halo feature: Only part of conductor (2) lies within the halo, only the capacitance between conductors (1) and part of conductor (2) within the halo is calculated, capacitance between (1) and (3) negligible and not included in the output netlist.

Domain decomposition technique consists of cutting the full layout into smaller sections, computing the capacitances in each domain and in domain overlap boundaries, then re-joining the parasitic netlists.

Rev. 092907_12