More About
IBIS Support:

Brochure (PDF) 468 KB

Brochure (HTML)

SmartSpice IBIS model support enables semiconductor component vendors to deliver SPICE accurate I/O buffer models for their IC products without disclosing SPICE parameters and transistor netlists. It enables PCB and system designers to accurately simulate high-speed interconnects required for signal integrity when using SmartSpice and semiconductor vendor supplied IBIS models.

General circuit diagram of IBIS devices in SmartSpice.

Key Features

• Enables semiconductor component vendors to deliver SPICE accurate I/O buffer models for their IC products without disclosing SPICE parameters and transistor netlists
• Enables PCB and system designers to accurately simulate high-speed interconnects for signal integrity using SmartSpice and semiconductor vendor supplied IBIS models
• Provides data for typical, minimum and maximum conditions, allowing worst case/best case analysis
• Provides a large amount of information for waveform and timing analysis for system verification
• Silvaco IBIS model support most of the common I/O structures: Input, Input_ECL, I/O, I/O_open_drain, I/O_open_sink, I/O_open_source, I/O_ECL, Output, Open_drain, Open_sink, Open_source, Output_ECL, 3-state, 3-state_ECL and Terminator
• Applicable to most digital components for designing high-speed interfaces (>600 MHz)
• Compatible with IBIS Open Forum specification V4.1 of January 2004

Rev. 101807_03