SILOS

Verilog Simulator

SILOS is an easy-to-use IEEE-1364-2001 compliant Verilog simulator used by leading IC designers. An industry standard since 1986, its powerful interactive debugging features provide today’s most productive design environment for FPGA, PLD, ASIC and custom digital designs.

Key Features

• IEEE-1364-2001 compliant Verilog simulator with Programming Language Interface (PLI) for SystemC™ support and other language extensions
• Productive debugging environment with graphic data analyzer, trace mode, hierarchy explorer, and interactive source code editor
• Full FPGA library support from leading vendors including Xilinx, Altera®, and QuickLogic
• Embedded lint tool that can make comprehensive syntax, semantic and design rule checking with over 500 checking rules. Can check for simulation and synthesis mismatches, race condition, clock domain synchronization and more
• Ensures comprehensive verification with integrated code coverage
• Supports compliance testing for RTCA/DO-254, "Design Assurance Guidance for Airborne Electronic Hardware", Appendix B

Rev 012010_20